Who am I?

I'm a Ph.D. student in the Department of Information Engineering, University of Pisa. I received both my Bachelor's and Master's Degrees from the Department of Computer Science, University of Pisa. During my Master Degree’s thesis, I started approaching the data stream processing research area. My main research interests are related to data stream processing applications in the networking domain, high performance network processing, data plane acceleration, SmartNICs and software defined networks. If you have any questions related to my work, please feel free to contact me.

Interests

  • Network monitoring
  • High-perfomance network processing
  • Data plane acceleration
  • Software Defined Networks
  • Data Stream Processing
  • Parallel computing

Education

  • Ph.D. in Information Engineering, currently enrolled

    University of Pisa

  • M.Sc. in Computer Science and Networking, 2019

    Scuola Superiore Sant'Anna and University of Pisa

  • B.Sc. in Computer Science, 2016

    University of Pisa

Publications

Data Stream Processing in Software Defined Networks: Perspectives and Challenges

The new paradigm of network softwarization is pushing programmability and programming abstractions as key elements at different levels …

Talks

Data Stream Processing in Software Defined Networks: Perspectives and Challenges

The talk is part of the Next Generation Networks session of the 2020 25th IEEE CAMAD Virtual Conference, and it aims at presenting our …

Optimizing Network Service Design Aspects in 5G and Beyond Scenario

In the context of 5G and Network Cloudification, latency is strongly influenced by both the data transmission delay and the time …

Enhancing Scalability in Software Defined Networks Throug Data Stream Processing

The talk aims at presenting my research project for the PhD program in Information Engineering. First of all, new generation networks …

Teaching

Wireless Networks course - Academic Year 2019/2020

Teaching support for the laboratory part of the course.

Research Projects and Contributions

WindFlow

Contribution to the WindFlow library, designed to perform parallel stream processing on shared-memory systems. This is a project of the Parallel Programming Models (PPMs) group at the Department of Computer Science, University of Pisa, Italy. My contribution mainly consists in the implementation of a benchmark composed by four real-time streaming applications in the fields of fraud detection, Internet of Things, vehicular traffic monitoring and word frequency analysis.

Thesis

Master's Thesis [2019] - Benchmarking Data Stream Processing Frameworks on Multicores

The work shows a comparison in terms of performance between traditional Data Stream Processing (DaSP) systems and WindFlow, an efficient C++17 streaming library based on FastFlow's building blocks. The goal is to quantify the benefit that may be achieved by using the C++ solution with respect to modern Java-based ones. A benchmark of four real-world DaSP applications have been designed and implementations are provided using Apache Storm, Apache Flink and WindFlow. Experiments show a significant throughput improvement and latency reduction by using the C++ solution with respect to the state-of-the-art frameworks on single multicore machines. The results obtained are encouraging for future works which aim at designing innovative DaSP frameworks based on C++ and providing high-level abstractions like Storm and Flink, that may be able to overcome modern Java-based Stream Processing Engines (SPEs) on distributed scenarios too. The entire work has been supervised by Dr. Gabriele Mencagli and contributes to the WindFlow project. The thesis document and the presentation are available in English at the following links. The developed code is open source and entirely accessible on GitHub (links below).

Bachelor's Thesis [2016] - Programming Techniques for FPGA Devices

The work has been supervised by Prof. Marco Danelutto and is a dissertation about FPGA (Field Programmable Gate Array) programming methodologies (Hardware Description Languages, Chisel and OpenCL), with an overview of current technological trends. Programming methologies offering a higher lever of abstraction with respect to the underlying hardware improve the usability aspect and extend the range of programmers which are able to access the technology. However, highering the abstraction level reflects in general in performance results that are worse with respect to the ones obtained by using a HDL approach. In order to design a good (in terms of performance) Verilog or VHDL program, an expert HDL programmer is needed, who is required to know all the architecture's details and must be able to exploit at best the low level constructs offered by the HDL in order to write well optimized code. Chisel is an example of high-level HDL which adds hardware construction primitives to the Scala programming language. The idea is to simplify the design of a parameterizable circuit by exploiting a modern programming language such as Scala and at the same time preserving the performance aspect by producing synthesizable Verilog code, generated from the Chisel modules. The OpenCL standard allows for the implementation of parallel algorithms that can guarantee portability among different platforms (CPUs, GPUs, FPGAs) with minimal recoding and inherently offers the ability of expressing parallel algorithms to be implemented on FPGAs at a much higher level of abstraction than HDLs. In fact, the OpenCL language is based on C programming language, enriched with extensions that allow for the specification of parallelism. Hence, the general trend is to reach optimal performance, or at least comparable to the one achievable by using low-level HDL approaches, and at the same time try to increase the abstraction level in order to expand the range of programmers that are able to access the FPGA technology. The thesis document and the presentation (links below) are both in Italian language.

Academic Projects

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Parallel and Distributed Systems (paradigms and models)

C++ and FastFlow implementation of the parallel scan Blelloch algorithm with a master-worker architecture schema and tests.

Programming Tools for Parallel and Distributed Systems

Exercises on MPI, TBB and OpenCL, including a C++ implementation of the Mandelbrot set computation using the Intel TBB library.

Networks and Technologies for Telecommunications - FPGA part

Verilog implementation of Adders, Subtractors and Multipliers.

Networks and Technologies for Telecommunications - SDN part

Portion of an In-Band Telemetry application to monitor the latency of packets traversing a certain path/tunnel established between two …

Packet Switching and Processing Architectures

C++ monitoring application that captures traffic with libpcap and identifies and analyses different flows.

Advanced Software Engineering

Collection of exercises on web services, business process modeling and containerization with Docker.

Advanced Programming

Collection of four projects using OCaml, Python and Java programming languages.

Network Management

Lua script that monitors system events with Sysdig to measure the performance of an application and the amount of resources required.

Programming Languages 2

Collection of four projects using OCaml and Java programming languages.

Computer Networks

Java implementation of a distributed chat system.

Contacts

Here you can find my office location and my contacts.

Department of Information Engineering, University of Pisa
Via Girolamo Caruso, 16
56122 Pisa (PI)
Italy